1. Field of the Invention
The present invention relates to an image signal processing circuit and, more particularly, to an image signal processing circuit with a multiple port memory.
2. Description of the Prior Art
An image processor typically includes a large number of processor elements (hereinafter named PE's) which, for example, may include digital computation circuits and which are arranged in a parallel formation. Several types of architectures have been proposed for use with the image processors, such as the systolic array method shown in FIG. 1 and the crossbar switch method shown in FIG. 2.
In the systolic array method, a large number of PE's are disposed as shown in FIG. 1, in which adjacent PE's are connected so as to enable communication therebetween. Such prior art has been disclosed in the publication of Japanese Patent Laid-Open No. SHO 56-123069.
In the crossbar switch method shown in FIG. 2, on the other hand, inputs IN1 to IN4 and the outputs OUT1 to OUT4 of PE81 to PE84, respectively, intersect the inputs of PE81 to PE84 and each intersection is used as a switch. By changing the connections of PE81 to PEB4 the internal structure of the image processor is varied.
In the image processor using the aforementioned crossbar switch method, to compensate for a delay between processors or between processor inputs, a memory should be disposed in each of PE81 to PE84. Further, a memory for storing a coefficient and a constant is required in each of PE81 to PE84.
Since, in a parallel processing arrangement, each of PE81 to PE84 does not directly access the contents of the memories in other PE's, the memories of PE81 to PE84 may redundantly store the same data.
Further, PE81 to PE84 normally have in the same structure. As a result, when a memory having a relatively large storage capacity is required for any of PE81 to PE84, this large size memory is used for each of PE81 to PE84. Thus, in memories of the processor elements may not be fully utilized, so that unused storage areas in several of the memories are typically present.
Thus, although the structure of the prior art processor can be varied so as to provide flexibility, memory areas are unused and a relatively high amount of circuit redundancy is present. Therefore, the prior art has failed to provide an image processor having adequate flexibility and a minimal amount of circuit redundancy.